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ATmega128
? Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
W hen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector
(See “Interrupts” on page 59 ) is executed when the TOV3 flag, located in ETIFR, is set.
? Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
W hen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare C Match Interrupt is enabled. The corresponding
interrupt vector (See “Interrupts” on page 59 ) is executed when the OCF3C flag, located in
ETIFR, is set.
? Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
W hen this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare C Match Interrupt is enabled. The corresponding
interrupt vector (See “Interrupts” on page 59 ) is executed when the OCF1C flag, located in
ETIFR, is set.
Timer/Counter
Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
– TIFR
Read/ W rite
Initial Value
OCF2
R/ W
0
TOV2
R/ W
0
ICF1
R/ W
0
OCF1A
R/ W
0
OCF1B
R/ W
0
TOV1
R/ W
0
OCF0
R/ W
0
TOV0
R/ W
0
TIFR
Note:
This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in
this section. The remaining bits are described in their respective timer sections.
? Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. W hen the Input Capture Register
(ICR1) is set by the W GMn3:0 to be used as the TOP value, the ICF1 flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
? Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
? Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
? Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the W GMn3:0 bits setting. In normal and CTC modes, the
TOV1 flag is set when the timer overflows. Refer to Table 61 on page 134 for the TOV1 flag
behavior when using another W GMn3:0 bit setting.
140
2467X–AVR–06/11
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